1. Field of the Invention
The present invention relates generally to a method of manufacturing semiconductor devices and, more specifically, to a method of manufacturing a capacitor with variable bottom cell plate (BCP) sidewall thickness.
2. Description of the Prior Art
Capacitors continue to have increasing aspect ratios in higher generation integrated circuitry fabrication. For example, dynamic random access memory (DRAM) capacitors now have elevations of from 1 to 3 microns, and widths of less than or equal to about 0.1 micron.
A common type of capacitor is a so-called container device. A storage electrode of such device is shaped as a container. Dielectric material and another capacitor electrode may be formed within the container and/or along an outer edge of the container, which can form a capacitor having high capacitance and a small footprint.
Container-shaped storage nodes are becoming increasingly taller and narrower (i.e., are being formed with higher aspect ratios) in an effort to achieve desired levels of capacitance while decreasing the amount of semiconductor real estate consumed by individual capacitors. Unfortunately, high aspect ratio container-shaped storage nodes can be structurally weak, and subject to toppling, twisting and/or breaking from an underlying base.
Exemplary methodology being developed to avoiding toppling of high aspect ratio containers is so-called lattice methodology. In such methodology, a lattice is provided to hold container-shaped electrodes from toppling, while leaving outer surfaces of the container-shaped electrodes exposed for utilization as capacitive surfaces of capacitors. During lattice methodology, container-shaped electrodes are formed in openings in a supporting material (such as, for example, borophosphosilicate glass (BPSG)), and then the supporting material is removed with an isotropic etch.
Unfortunately, conventional lattice methodology alone is not enough to prevent toppling, twisting and breaking of container-shaped storage nodes formed with increasingly high aspect ratios. Furthermore, in order to meet cell capacitance requirements for advanced DRAM technologies, larger and improved capacitance is always required. Accordingly, it is desired to develop new storage node structures, and new methods for forming storage node structures.